{"id":4123,"date":"2024-11-08T14:50:35","date_gmt":"2024-11-08T13:50:35","guid":{"rendered":"https:\/\/web.infn.it\/TechTransfer\/portfolio_page\/cam-memory\/"},"modified":"2026-01-13T14:30:24","modified_gmt":"2026-01-13T13:30:24","slug":"cam-memory","status":"publish","type":"portfolio_page","link":"https:\/\/web.infn.it\/TechTransfer\/en\/portfolio_page\/cam-memory\/","title":{"rendered":"CAM Memory"},"content":{"rendered":"

[vc_row css_animation=”” row_type=”row” use_row_as_full_screen_section=”no” type=”full_width” angled_section=”no” text_align=”left” background_image_as_pattern=”without_pattern”][vc_column][vc_raw_html]W3dwc2VvX2JyZWFkY3J1bWJd[\/vc_raw_html][vc_empty_space][vc_column_text]<\/p>\n

CAM Memory<\/span><\/h1>\n

[\/vc_column_text][vc_empty_space][\/vc_column][\/vc_row][vc_row css_animation=”” row_type=”row” use_row_as_full_screen_section=”no” type=”full_width” angled_section=”no” text_align=”left” background_image_as_pattern=”without_pattern”][vc_column width=”2\/3″][vc_empty_space][vc_column_text]Content Addressable Memory (CAM) cells developed to be integrated into chips that can be used to solve pattern recognition problems, such as DNA sequence analysis or image recognition.[\/vc_column_text][vc_empty_space][vc_single_image image=”4124″ img_size=”full” qode_css_animation=””][vc_empty_space][vc_column_text]<\/p>\n

How does it work?<\/span><\/h3>\n

[\/vc_column_text][vc_empty_space][vc_column_text]The CAM memory architecture is designed to reduce the length of the data lines and consequently reduce the energy consumption linked with the propagation of data over the lines. In addition, a matching circuit enables the reduction of the consumption linked with the search phase, ensuring an optimization in the comparison between the data present and the data entered. If one of the bits of the entered word does not find a match, the cell sends a kill signal that inhibits the switching of downstream cells. Thanks to this feature, the cell matrix requires less than 0.4 fJ\/bit for comparison in HPC (High Power Computing) technologies and less than 0.2 fJ\/bit for HPL (High Power Low-leakage) technologies. The CAM cell was designed in two variants, in 28 nm CMOS technology using a fully-CMOS approach. A prototype containing these cells was manufactured and tested, up to 400 MHz, confirming the expected performance.[\/vc_column_text][vc_empty_space][vc_column_text]<\/p>\n

Applications<\/span><\/h3>\n

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