{"id":4655,"date":"2024-09-23T14:17:25","date_gmt":"2024-09-23T12:17:25","guid":{"rendered":"https:\/\/web.infn.it\/TechTransfer\/portfolio_page\/fpga-based-reconfigurable-hadronic-fluence-sensor\/"},"modified":"2026-02-04T12:01:37","modified_gmt":"2026-02-04T11:01:37","slug":"fpga-based-reconfigurable-hadronic-fluence-sensor","status":"publish","type":"portfolio_page","link":"https:\/\/web.infn.it\/TechTransfer\/en\/portfolio_page\/fpga-based-reconfigurable-hadronic-fluence-sensor\/","title":{"rendered":"FPGA-based reconfigurable hadronic fluence sensor"},"content":{"rendered":"

[vc_row css_animation=”” row_type=”row” use_row_as_full_screen_section=”no” type=”full_width” angled_section=”no” text_align=”left” background_image_as_pattern=”without_pattern”][vc_column][vc_raw_html]W3dwc2VvX2JyZWFkY3J1bWJd[\/vc_raw_html][vc_empty_space][vc_column_text]<\/p>\n

FPGA-based reconfigurable hadronic fluence sensor<\/span><\/h1>\n

[\/vc_column_text][vc_empty_space][\/vc_column][\/vc_row][vc_row css_animation=”” row_type=”row” use_row_as_full_screen_section=”no” type=”full_width” angled_section=”no” text_align=”left” background_image_as_pattern=”without_pattern”][vc_column width=”2\/3″][vc_empty_space][vc_column_text]Ionizing particle detector that incorporates both the sensitive element and the readout logic in a single FPGA (Field-Programmable Gate Array) chip and can be reprogrammed and configured.[\/vc_column_text][vc_empty_space][vc_single_image image=”4657″ img_size=”full” qode_css_animation=””][vc_empty_space][vc_column_text]<\/p>\n

How does it work?<\/span><\/h3>\n

[\/vc_column_text][vc_empty_space][vc_column_text]Ionizing particles can cause a state change (Single Event Upset) in microelectronic devices such as static RAM memories (SRAM). The number of events is proportional to that of ionizing particles, so it is possible to use SRAM memories as fluence monitors. <\/p>\n

A limitation of this approach is that separate components are needed to detect upsets and to read them, and the resulting system is therefore complicated and expensive; moreover, the readout logic is usually fixed and not reconfigurable.<\/p>\n

In this invention, a single FPGA component implements both the sensitive element and the readout logic, which can also be programmed and reconfigured.[\/vc_column_text][vc_empty_space][vc_column_text]<\/p>\n

Applications<\/span><\/h3>\n

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